1. Field of the Invention
The invention relates to semiconductor devices, and more particularly, to semiconductor devices comprising a higher density cell area having a plurality of capacitors including, for example, projecting lower electrodes, adjacent a lower density peripheral region and methods of manufacturing the same.
2. Description of the Related Art
Due to the technical requirements associated with achieving higher degrees of integration in semiconductor devices, there has been continuing emphasis on reducing the surface area required for forming a memory cell in semiconductor memory devices. These efforts have led to difficulties in forming capacitors having a sufficient storage capacitance within the memory cell. Various methods have been proposed and/or adopted for maintaining the capacitance of such storage capacitors at acceptable levels in a reduced cell area. One approach involves increasing the height of the storage node by, for example, increasing the height of the lower electrode of a capacitor to form what is widely referred to as a cylindrical capacitor.
Examples of such cylindrical capacitor structures are disclosed in U.S. Pat. Nos. 6,700,153 and 6,171,902, the disclosures of which are hereby incorporated, in their entirety, by reference.
FIG. 1 is a cross sectional view illustrating a semiconductor device that includes a cylindrical capacitor. FIGS. 2A and 2B are cross sectional views illustrating various processing steps according to a method of forming the cylindrical capacitor as shown in FIG. 1. As illustrated in FIG. 1, the semiconductor device includes a capacitor 22 formed on a substrate 10 that includes a cell area in which the memory cells are formed and a peripheral area in which other associated circuitry will be formed. Although not shown, those of skill in the art will appreciate that the semiconductor device also includes a number of other underlying structures including, for example, wells, isolation regions, gate patterns and bit lines, formed on the substrate 10.
A first insulation interlayer 12 is formed on the substrate 10, and a contact pad 14 is formed through the first insulation interlayer 12 in the cell area of the substrate 10. The capacitor 22 includes a cylindrical lower electrode 16, a dielectric layer 18 formed on the cylindrical lower electrode 16 and an upper electrode 20 formed on the dielectric layer 18. The contact pad 14 is electrically connected to a lower electrode of the capacitor 22, and a second insulation interlayer 24 is formed on the capacitor 22.
The cylindrical capacitor 22 is formed in the cell area of the substrate 10, and a mold pattern 26 in the peripheral area of the substrate 10 is removed simultaneously when the mold pattern 26 in the cell area and the sacrificial layer 28 are removed after a node separation of the lower electrodes as shown in FIGS. 2A and 2B. As a result, as illustrated in FIG. 1, the second insulation interlayer 24 exhibits a large step difference between the cell area and the peripheral area of the substrate.
This step difference results when the second insulation interlayer 24 in the peripheral area of the substrate 10 is formed directly on the first insulation interlayer 12 while the second insulation interlayer 24 in the cell area of the substrate 10 is formed on the upper electrode 20 of the capacitor 22, thereby producing a step difference corresponding to the relative height difference between the surface in the cell area and the surface in the peripheral area of the substrate 10. Accordingly, the step difference exhibited by the second insulation interlayer 24 corresponds to the height of the capacitor 22.
However, this large step difference in the second insulation interlayer 24 increases the likelihood of various processing and/or patterning defects during the manufacture of semiconductor devices that include a cylindrical capacitor. An additional process, for example, a chemical mechanical polishing (CMP) process, may been utilized for reducing or removing the step difference from the surface of the second insulation interlayer 24. However, the inclusion of one or more additional process steps requires additional time and increases the cost of manufacturing such semiconductor devices.
Accordingly, a need remains for an improved method of reducing or removing the step difference from the surface of an insulation interlayer formed on a semiconductor substrate that includes a cell area having cylindrical capacitors and an adjacent peripheral region.